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Explain the difference between register-to-register, register-to-memory, and memory-to-memory instructions.
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Several design decisions exist with regard to instruction sets. Name four and explain.
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What is an expanding opcode?
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If a byte-addressable machine with 32-bit words stores the hex value 98765432, indicate how this value would be stored on a little endian machine and on a big endian machine. Why does "endian-ness" matter?
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We can design stack architectures, accumulator architectures, or general-purpose register architectures. Explain the differences between these choices and give some situations where one might be better than another.
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How do memory-memory, register-memory, and load-store architectures differ? How are they the same?
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What are the pros and cons of fixed-length and variable-length instructions? Which is currently more popular?
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How does an architecture based on zero operands ever get any data values from memory?
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Which is likely to be longer (have more instructions): a program written for a zero-address architecture, a program written for a one-address architecture, or a program written for a two-address architecture? Why?
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Why might stack architectures represent arithmetic expressions in reverse Polish notation?
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Name the seven types of data instructions and explain each.
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What is an address mode?
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Give examples of immediate, direct, register, indirect, register indirect, and indexed addressing.
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How does indexed addressing differ from based addressing?
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Why do we need so many different addressing modes?
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Explain the concept behind pipelining.
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What is the theoretical speedup for a 4-stage pipeline with a 20ns clock cycle if it is processing 100 tasks?
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What are the pipeline conflicts that can cause a slowdown in the pipeline?
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What are the two types of ILP and how do they differ?
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Explain superscalar, superpipelining, and VLIW architectures.
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List several ways in which the Intel and MIPS ISAs differ. Name several ways in which they are the same.
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Explain Java bytecodes.
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Give an example of a current stack-based architecture and a current GPR-based architecture. How do they differ?